Specifications

Altera Corporation 8–75
October 2007 Nios II Processor Reference Handbook
mulxuu
mulxuu
multiply extended unsigned/unsigned
Operation:
rC
←
((unsigned) rA) × ((unsigned) rB))
63..32
Assembler Syntax:
mulxuu rC, rA, rB
Example:
mulxuu r6, r7, r8
Description:
Treating rA and rB as unsigned integers,
mulxuu multiplies rA times rB and
stores the 32 high-order bits of the product to rC.
Nios II processors that do not implement the
mulxss instruction cause an
unimplemented-instruction exception.
Usage:
Use
mulxuu and mul to compute the 64-bit product of two 32-bit unsigned
integers. Furthermore,
mulxuu can be used as part of the calculation of a 128-
bit product of two 64-bit signed integers. Given two 64-bit signed integers, each
contained in a pair of 32-bit registers, (S1 : U1) and (S2 : U2), their 128-bit
product is (U1 × U2) + ((S1 × U2) << 32) + ((U1 × S2) << 32) + ((S1 × S2) << 64).
The
mulxuu and mul instructions are used to calculate the 64-bit product
U1 × U2.
mulxuu also can be used as part of the calculation of a 128-bit product of two
64-bit unsigned integers. Given two 64-bit unsigned integers, each contained in
a pair of 32-bit registers, (T1 : U1) and (T2 : U2), their 128-bit product is (U1 ×
U2) + ((U1 × T2) << 32) + ((T1 × U2) << 32) + ((T1 × T2) << 64). The
mulxuu
and
mul instructions are used to calculate the four 64-bit products U1 × U2, U1
× T2, T1 × U2, and T1 × T2.
Instruction Type: R
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
C = Register index of operand rC
313029282726252423222120191817161514131211109876543210
ABC0x0700x3a