Specifications

Table Of Contents
Altera Corporation 8–65
October 2007 Nios II Processor Reference Handbook
ldw / ldwio
ldw / ldwio
load 32-bit word from memory or I/O peripheral
Operation:
rB
Mem32[rA + σ (IMM14)]
Assembler Syntax:
ldw rB, byte_offset(rA)
ldwio rB, byte_offset(rA)
Example:
ldw r6, 100(r5)
Description: Computes the effective byte address specified by the sum of rA and the instruction's
signed 16-bit immediate value. Loads register rB with the memory word located at the
effective byte address. The effective byte address must be word aligned. If the byte
address is not a multiple of 4, the operation is undefined.
Usage: In processors with a data cache, this instruction may retrieve the desired data from the
cache instead of from memory. Use the
ldwio instruction for peripheral I/O. In
processors with a data cache,
ldwio bypasses the cache and memory. Use the
ldwio instruction for peripheral I/O. In processors with a data cache, ldwio
bypasses the cache and is guaranteed to generate an Avalon-MM data transfer. In
processors without a data cache,
ldwio acts like ldw.
For more information on data cache, see the Cache and Tightly-Coupled Memory
chapter of the Nios II Software Developer's Handbook.
Instruction Type: I
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
313029282726252423222120191817161514131211109876543210
A B IMM16 0x17
Instruction format for
ldw
313029282726252423222120191817161514131211109876543210
A B IMM16 0x37
Instruction format for
ldwio