Specifications

Altera Corporation 8–63
October 2007 Nios II Processor Reference Handbook
ldh / ldhio
ldh / ldhio
load halfword from memory or I/O peripheral
Operation:
rB
←
σ (Mem16[rA + σ (IMM16)])
Assembler Syntax:
ldh rB, byte_offset(rA)
ldhio rB, byte_offset(rA)
Example:
ldh r6, 100(r5)
Description: Computes the effective byte address specified by the sum of rA and the instruction's
signed 16-bit immediate value. Loads register rB with the memory halfword located at
the effective byte address, sign extending the 16-bit value to 32 bits. The effective byte
address must be halfword aligned. If the byte address is not a multiple of 2, the
operation is undefined.
Usage: In processors with a data cache, this instruction may retrieve the desired data from the
cache instead of from memory. Use the
ldhio instruction for peripheral I/O. In
processors with a data cache,
ldhio bypasses the cache and is guaranteed to
generate an Avalon-MM data transfer. In processors without a data cache,
ldhio acts
like
ldh.
For more information on data cache, see the Cache and Tightly-Coupled Memory
chapter of the Nios II Software Developer's Handbook.
Instruction Type: I
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
313029282726252423222120191817161514131211109876543210
A B IMM16 0x0f
Instruction format for
ldh
313029282726252423222120191817161514131211109876543210
A B IMM16 0x2f
Instruction format for
ldhio