Specifications

8–62 Altera Corporation
Nios II Processor Reference Handbook October 2007
ldbu / ldbuio
ldbu / ldbuio
load unsigned byte from memory or I/O peripheral
Operation:
rB
←
0x000000 : Mem8[rA + σ (IMM16)]
Assembler Syntax:
ldbu rB, byte_offset(rA)
ldbuio rB, byte_offset(rA)
Example:
ldbu r6, 100(r5)
Description: Computes the effective byte address specified by the sum of rA and the instruction's
signed 16-bit immediate value. Loads register rB with the desired memory byte, zero
extending the 8-bit value to 32 bits.
Usage: In processors with a data cache, this instruction may retrieve the desired data from the
cache instead of from memory. Use the
ldbuio instruction for peripheral I/O. In
processors with a data cache,
ldbuio bypasses the cache and is guaranteed to
generate an Avalon-MM data transfer. In processors without a data cache,
ldbuio
acts like
ldbu.
For more information on data cache, see the Cache and Tightly-Coupled Memory
chapter of the Nios II Software Developer's Handbook.
Instruction Type: I
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
IMM16 = 16-bit signed immediate value
313029282726252423222120191817161514131211109876543210
A B IMM16 0x03
Instruction format for
ldbu
313029282726252423222120191817161514131211109876543210
A B IMM16 0x23
Instruction format for
ldbuio