Specifications

Altera Corporation 1–3
October 2007 Nios II Processor Reference Handbook
Introduction
Figure 1–1. Example of a Nios II Processor System
If the prototype system adequately meets design requirements using an
Altera-provided reference design, you can copy the reference design and
use it as-is in the final hardware platform. Otherwise, you can customize
the Nios II processor system until it meets cost or performance
requirements.
Customizing
Nios II
Processor
Designs
In practice, most FPGA designs implement some extra logic in addition
to the processor system. Altera FPGAs provide flexibility to add features
and enhance performance of the Nios II processor system. Conversely,
you can eliminate unnecessary processor features and peripherals to fit
the design in a smaller, lower-cost device.
Nios II
Processor Core
SDRAM
Controller
On-Chip ROM
Tristate bridge to
off-chip memory
Avalon Switch Fabric
JTAG
Debug Module
SDRAM
Memory
Flash
Memory
SRAM
Memory
UART
Timer1
Timer2
LCD Display Driver
General-Purpose I/O
Ethernet Interface
CompactFlash
Interface
LCD
Screen
Ethernet
MAC/PHY
Compact
Flash
Buttons,
LEDs, etc.
TXD
RXD
JTAG connection
to software debugger
Clock
Reset
Data
Inst.