Specifications

Altera Corporation 8–51
October 2007 Nios II Processor Reference Handbook
divu
divu
divide unsigned
Operation:
rC
←
rA ÷ rB
Assembler Syntax:
divu rC, rA, rB
Example:
divu r6, r7, r8
Description: Treating rA and rB as unsigned integers, this instruction divides rA by rB and then
stores the integer portion of the resulting quotient to rC. After attempted division by
zero, the value of rC is undefined. There is no divide-by-zero exception.
Nios II processors that do not implement the
divu instruction cause an
unimplemented-instruction exception.
Usage: Remainder of Division:
If the result of the division is defined, then the remainder can be computed in rD using
the following instruction sequence:
divu rC, rA, rB
mul rD, rC, rB
sub rD, rA, rD
; The original divu operation
; rD = remainder
Instruction Type: R
Instruction Fields: A = Register index of operand rA
B = Register index of operand rB
C = Register index of operand rC
313029282726252423222120191817161514131211109876543210
ABC0x2400x3a