Specifications

Altera Corporation 1–1
October 2007
1. Introduction
Introduction
This chapter is an introduction to the Nios
®
II embedded processor
family. This chapter helps hardware and software engineers understand
the similarities and differences between the Nios II processor and
traditional embedded processors.
This chapter contains the following sections:
■ “Nios II Processor System Basics” on page 1–1
■ “Getting Started with the Nios II Processor” on page 1–2
■ “Customizing Nios II Processor Designs” on page 1–3
■ “Configurable Soft-Core Processor Concepts” on page 1–4
■ “OpenCore Plus Evaluation” on page 1–6
Nios II
Processor
System Basics
The Nios II processor is a general-purpose RISC processor core,
providing:
■ Full 32-bit instruction set, data path, and address space
■ 32 general-purpose registers
■ 32 external interrupt sources
■ Single-instruction 32 × 32 multiply and divide producing a 32-bit
result
■ Dedicated instructions for computing 64-bit and 128-bit products of
multiplication
■ Floating-point instructions for single-precision floating-point
operations
■ Single-instruction barrel shifter
■ Access to a variety of on-chip peripherals, and interfaces to off-chip
memories and peripherals
■ Hardware-assisted debug module enabling processor start, stop,
step and trace under integrated development environment (IDE)
control
■ Software development environment based on the GNU C/C++ tool
chain and Eclipse IDE
■ Integration with Altera
®
's SignalTap
®
II logic analyzer, enabling real-
time analysis of instructions and data along with other signals in the
FPGA design
■ Instruction set architecture (ISA) compatible across all Nios II
processor systems
■ Performance up to 250 DMIPS
NII51001-7.2.0