Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

Altera Corporation 8–25
October 2007 Nios II Processor Reference Handbook
break
break
debugging breakpoint
Operation:
bstatus
←
status
PIE
←
0
U
←
0
ba
←
PC + 4
PC
←
break handler address
Assembler Syntax:
break
break imm5
Example:
break
Description: Breaks program execution and transfers control to the debugger break-processing
routine. Saves the address of the next instruction in register
ba and saves the contents
of the
status register in bstatus. Disables interrupts, then transfers execution to
the break handler.
The 5-bit immediate field
imm5 is ignored by the processor, but it can be used by the
debugger.
break with no argument is the same as break 0.
Usage:
break is used by debuggers exclusively. Only debuggers should place break in a
user program, operating system, or exception handler. The address of the break
handler is specified at system generation time.
Some debuggers support break and break 0 instructions in source code. These
debuggers treat the
break instruction as a normal breakpoint.
Instruction Type: R
Instruction Fields: IMM5 = Type of breakpoint
313029282726252423222120191817161514131211109876543210
0 0 0x1e 0x34 IMM5 0x3a