Specifications

8–8 Altera Corporation
Nios II Processor Reference Handbook October 2007
Instruction Set Reference
Instruction Set
Reference
The following pages list all Nios II instruction mnemonics in alphabetical
order. Table 8–5 shows the notation conventions used to describe
instruction operation.
Table 8–5. Notation Conventions
Notation Meaning
X
←
Y
X is written with Y
PC
←
X
The program counter (PC) is written with address X; the
instruction at X will be the next instruction to execute
PC The address of the assembly instruction in question
rA, rB, rC One of the 32-bit general-purpose registers
IMMn An n-bit immediate value, embedded in the instruction word
IMMED An immediate value
X
n
The n
th
bit of X, where n = 0 is the LSB
X
n..m
Consecutive bits n through m of X
0xNNMM Hexadecimal notation
X : Y Bitwise concatenation
For example, (0x12 : 0x34) = 0x1234
σ(X) The value of X after being sign-extended into a full register-
sized signed integer
X >> n The value X after being right-shifted n bit positions
X << n The value X after being left-shifted n bit positions
X & Y Bitwise logical AND
X | Y Bitwise logical OR
X ^ Y Bitwise logical XOR
~X Bitwise logical NOT (one’s complement)
Mem8[X] The byte located in data memory at byte-address X
Mem16[X] The halfword located in data memory at byte-address X
Mem32[X] The word located in data memory at byte-address X
label An address label specified in the assembly file
(signed) rX The value of rX treated as a signed number
(unsigned) rX The value of rX, treated as an unsigned number