Specifications
Table Of Contents
- Nios II Processor Reference Handbook
- Contents
- Chapter Revision Dates
- About This Handbook
- Section I. Nios II Processor
- 1. Introduction
- 2. Processor Architecture
- 3. Programming Model
- Introduction
- General- Purpose Registers
- Control Registers
- Operating Modes
- Exception Processing
- Memory and Peripheral Access
- Instruction Set Categories
- Referenced Documents
- Document Revision History
- 4. Instantiating the Nios II Processor in SOPC Builder
- Section II. Appendices
- 5. Nios II Core Implementation Details
- Introduction
- Device Family Support
- Nios II/f Core
- Nios II/s Core
- Nios II/e Core
- Referenced Documents
- Document Revision History
- 6. Nios II Processor Revision History
- 7. Application Binary Interface
- 8. Instruction Set Reference
- Introduction
- Word Formats
- Instruction Opcodes
- Assembler Pseudo- instructions
- Assembler Macros
- Instruction Set Reference
- add
- addi
- and
- andhi
- andi
- beq
- bge
- bgeu
- bgt
- bgtu
- ble
- bleu
- blt
- bltu
- bne
- br
- break
- bret
- call
- callr
- cmpeq
- cmpeqi
- cmpge
- cmpgei
- cmpgeu
- cmpgeui
- cmpgt
- cmpgti
- cmpgtu
- cmpgtui
- cmple
- cmplei
- cmpleu
- cmpleui
- cmplt
- cmplti
- cmpltu
- cmpltui
- cmpne
- cmpnei
- custom
- div
- divu
- eret
- flushd
- flushda
- flushi
- flushp
- initd
- initi
- jmp
- jmpi
- ldb / ldbio
- ldbu / ldbuio
- ldh / ldhio
- ldhu / ldhuio
- ldw / ldwio
- mov
- movhi
- movi
- movia
- movui
- mul
- muli
- mulxss
- mulxsu
- mulxuu
- nextpc
- nop
- nor
- or
- orhi
- ori
- rdctl
- ret
- rol
- roli
- ror
- sll
- slli
- sra
- srai
- srl
- srli
- stb / stbio
- sth / sthio
- stw / stwio
- sub
- subi
- sync
- trap
- wrctl
- xor
- xorhi
- xori
- Referenced Documents
- Document Revision History

Altera Corporation 6–7
October 2007 Nios II Processor Reference Handbook
Nios II Processor Revision History
Table 6–6 lists revisions to the JTAG debug module.
Referenced
Documents
This chapter references no other documents.
Table 6–6. JTAG Debug Module Revisions
Version Release Date Notes
7.2 October 2007 No changes.
7.1 May 2007 No changes.
7.0 March 2007 No changes.
6.1 November 2006 No changes.
6.0 May 2006 No changes.
5.1 October 2005 No changes.
5.0 May 2005 Full support for HardCopy devices (previous versions of the JTAG debug
module did not support HardCopy devices).
1.1 December 2004 Bug fix:
When using the Nios II/s and Nios II/f cores, hardware breakpoints may
have falsely triggered when placed on the instruction sequentially following
a
jmp, trap, or any branch instruction.
1.01 September 2004
● Feature enhancements:
(1) Added the ability to trigger based on the instruction address. Uses
include triggering trace control (trace on/off), sequential triggers (see
below), and trigger in/out signal generation.
(2) Enhanced trace collection such that collection can be stopped when
the trace buffer is full without halting the Nios II processor.
(3) Armed triggers – Enhanced trigger logic to support two levels of
triggers, or "armed triggers"; enabling the use of "Event A then event B"
trigger definitions.
● Bug fixes:
(1) On the Nios II/s core, trace data sometimes recorded incorrect
addresses during interrupt processing.
(2) Under certain circumstances, captured trace data appeared to start
earlier or later than the desired trigger location.
(3) During debug, the processor would hang if a hardware breakpoint
and an interrupt occurred simultaneously.
1.0 May 2004
Initial release of the JTAG debug module
.