Specifications

6–4 Altera Corporation
Nios II Processor Reference Handbook October 2007
Core Revisions
5.1 SP1 January 2006 Bug Fix:
Back-to-back store instructions can cause memory corruption to the
stored data. If the first store is not to the last word of a cache line and the
second store is to the last word of the line, memory corruption occurs.
5.1 October 2005 No changes.
5.0 May 2005
● Added optional tightly-coupled memory ports. Designers can add zero
to four tightly-coupled instruction master ports, and zero to four tightly-
coupled data master ports.
● Made the data cache line size configurable. Designers can configure
the data cache with the following line sizes: 4, 16, or 32 bytes.
Previously, the data cache line size was fixed at 4 bytes.
● Made instruction and data caches optional (previously, cache
memories were always present). If the instruction cache is not present,
the Nios II core does not have an instruction master port, and must use
a tightly-coupled instruction memory.
● Full support for HardCopy devices (previous versions required a work
around to support HardCopy devices).
1.1 December 2004
● Added user-configurable options affecting multiply and shift
operations. Now designers can choose one of three options:
(1) Use embedded multiplier resources available in the target device
family (previously available).
(2) Use logic elements to implement multiply and shift hardware (new
option).
(3) Omit multiply hardware. Shift operations take one cycle per bit
shifted; multiply operations are emulated in software (new option).
● Added cpuid control register.
● Bug Fix:
Interrupts that were disabled by
wrctl ienable remained enabled
for one clock cycle following the
wrctl instruction. Now the
instruction following such a
wrctl cannot be interrupted.
1.01 September 2004
● Bug Fixes:
(1) When a store to memory is followed immediately in the pipeline by
a load from the same memory location, and the memory location is
held in d-cache, the load may return invalid data.This situation can
occur in C code compiled with optimization off (-O0).
(2) The SOPC Builder top-level system module included an extra,
unnecessary output port for systems with very small address spaces.
1.0 May 2004 Initial release of the Nios II/f core.
Table 6–3. Nios II/f Core Revisions
Version Release Date Notes