Specifications

Altera Corporation 6–1
October 2007
6. Nios II Processor Revision
History
Introduction
Each release of the Nios
®
II Embedded Design Suite (EDS) introduces
improvements to the Nios II processor, the software development tools,
or both. This document catalogs the history of revisions to the Nios II
processor; it does not track revisions to development tools, such as the
Nios II IDE. This chapter contains the following sections:
■ “Nios II Versions” on page 6–1
■ “Architecture Revisions” on page 6–2
■ “Core Revisions” on page 6–3
■ “JTAG Debug Module Revisions” on page 6–6
Improvements to the Nios II processor might affect:
■ Features of the Nios II architecture – An example of an architecture
revision is adding instructions to support floating-point arithmetic.
■ Implementation of a specific Nios II core – An example of a core revision
is increasing the maximum possible size of the data cache memory
for the Nios II/f core.
■ Features of the JTAG debug module – An example of a JTAG debug
module revision is adding an additional trigger input to the JTAG
debug module, allowing it to halt processor execution on a new type
of trigger event.
Altera implements Nios II revisions such that code written for an existing
Nios II core also works on future revisions of the same core.
Nios II Versions
The number for any version of the Nios II processor is determined by the
version of the Nios II EDS. For example, in the Nios II EDS version 7.2, all
Nios II cores are also version 7.2.
NII51018-7.2.0