Specifications

Altera Corporation 5–19
October 2007 Nios II Processor Reference Handbook
Nios II Core Implementation Details
Nios II/e Core
The Nios II/e “economy” core is designed to achieve the smallest
possible core size. Altera designed the Nios II/e core with a singular
design goal: Reduce resource utilization any way possible, while still
maintaining compatibility with the Nios II instruction set architecture.
Hardware resources are conserved at the expense of execution
performance. The Nios II/e core is roughly half the size of the Nios II/s
core, but the execution performance is substantially lower.
The resulting core is optimal for cost-sensitive applications, as well as
applications that require simple control logic.
Overview
The Nios II/e core:
■ Executes at most one instruction per six clock cycles
■ Can access up to 2 Gbytes of external address space
■ Supports the addition of custom instructions
■ Supports the JTAG debug module
■ Does not provide hardware support for potential unimplemented
instructions
■ Has no instruction cache or data cache
■ Does not perform branch prediction
The following sections discuss the noteworthy details of the Nios II/e
core implementation. This document does not discuss low-level design
issues, or implementation details that do not affect Nios II hardware or
software designers.
Arithmetic Logic Unit
The Nios II/e core does not provide hardware support for any of the
potential unimplemented instructions. All unimplemented instructions
are emulated in software.
The Nios II/e core employs dedicated shift circuitry to perform shift and
rotate operations. The dedicated shift circuitry achieves one-bit-per-cycle
shift and rotate operations.
Memory Access
The Nios II/e core does not provide instruction cache or data cache. All
memory and peripheral accesses generate an Avalon-MM transfer. The
Nios II/e core can address up to 2 Gbytes of external memory. The Nios II
architecture reserves the most-significant bit of data addresses for the bit-
31 cache bypass method. In the Nios II/e core, bit 31 is always zero.