Specifications

5–18 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/s Core
Exception Handling
The Nios II/s core supports the following exception types:
■ Hardware interrupt
■ Software trap
■ Unimplemented instruction
JTAG Debug Module
The Nios II/s core supports the JTAG debug module to provide a JTAG
interface to software debugging tools. The Nios II/s core supports an
optional enhanced interface that allows real-time trace data to be routed
out of the processor and stored in an external debug probe.
Unsupported Features
The Nios II/s core does not handle the execution of instructions with
undefined opcodes. If the processor issues an instruction word with an
undefined opcode, the resulting behavior is undefined.
Branch (correctly predicted not taken) 1
Branch (mispredicted) 4 Pipeline flush
trap, break, eret, bret,
flushp, wrctl, unimplemented
4 Pipeline flush
jmp, jmpi, ret, call, callr
4 Pipeline flush
rdctl
1
load,
store
> 1
flushi, initi
4
Multiply (1)
Divide (1)
Shift/rotate (with hardware multiply using embedded multipliers) 3
Shift/rotate (with hardware multiply using LE-based multipliers) 4
Shift/rotate (without hardware multiply present) 1 to 32
All other instructions 1
Note to Table 5–10:
(1) Depends on the hardware multiply or divide option. See Table 5–7 on page 13 for details.
Table 5–10. Instruction Execution Performance for Nios II/s Core (Part 2 of 2)
Instruction Cycles Penalties