Specifications

Altera Corporation 5–17
October 2007 Nios II Processor Reference Handbook
Nios II Core Implementation Details
Pipeline Stalls
The pipeline is set up so that if a stage stalls, no new values enter that
stage or any earlier stages. No “catching up” of pipeline stages is allowed,
even if a pipeline stage is empty.
Only the M-stage is allowed to create stalls.
The M-stage stall occurs if any of the following conditions occurs:
■ An M-stage load/store instruction is waiting for Avalon-MM data
master transfer to complete.
■ An M-stage shift/rotate instruction is still performing its operation
when using the multi-cycle shift circuitry (i.e., when the hardware
multiplier is not available).
■ An M-stage shift/rotate/multiply instruction is still performing its
operation when using the hardware multiplier (which takes three
cycles).
■ An M-stage multi-cycle custom instruction is asserting its stall signal.
This only occurs if the design includes multi-cycle custom
instructions.
Branch Prediction
The Nios II/s core performs static branch prediction to minimize the
cycle penalty associated with taken branches.
Instruction Performance
All instructions take one or more cycles to execute. Some instructions
have other penalties associated with their execution. Instructions that
flush the pipeline cause up to three instructions after them to be
cancelled. This creates a three-cycle penalty and an execution time of four
cycles. Instructions that require an Avalon-MM transfer are stalled until
the transfer completes.
Execution performance for all instructions is shown in Table 5–10.
Table 5–10. Instruction Execution Performance for Nios II/s Core (Part 1 of 2)
Instruction Cycles Penalties
Normal ALU instructions (e.g., add, cmplt)
1
Combinatorial custom instructions 1
Multi-cycle custom instructions 1
Branch (correctly predicted taken) 2