Specifications

5–16 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/s Core
Accessing tightly-coupled memory bypasses cache memory. The
processor core functions as if cache were not present for the address span
of the tightly-coupled memory. Instructions for managing cache, such as
initi and flushi, do not affect the tightly-coupled memory, even if the
instruction specifies an address in tightly-coupled memory.
Execution Pipeline
This section provides an overview of the pipeline behavior for the benefit
of performance-critical applications. Designers can use this information
to minimize unnecessary processor stalling. Most application
programmers never need to analyze the performance of individual
instructions, and live happy lives without ever studying Table 5–9.
The Nios II/s core employs a 5-stage pipeline. The pipeline stages are
listed in Table 5–9.
Up to one instruction is dispatched and/or retired per cycle. Instructions
are dispatched and retired in-order. Static branch prediction is
implemented using the branch offset direction; a negative offset
(backward branch) is predicted as taken, and a positive offset (forward
branch) is predicted as not-taken. The pipeline stalls for the following
conditions:
■ Multi-cycle instructions (e.g., shift/rotate without hardware
multiply)
■ Avalon-MM instruction master port read accesses
■ Avalon-MM data master port read/write accesses
■ Data dependencies on long latency instructions (e.g., load, multiply,
shift operations)
Table 5–9. Implementation Pipeline Stages for Nios II/s Core
Stage Letter Stage Name
FFetch
D Decode
EExecute
M Memory
W Writeback