Specifications

Altera Corporation 5–15
October 2007 Nios II Processor Reference Handbook
Nios II Core Implementation Details
Instruction Cache
The instruction cache for the Nios II/s core is nearly identical to the
instruction cache in the Nios II/f core. The instruction cache memory has
the following characteristics:
■ Direct-mapped cache implementation
■ The instruction master port reads an entire cache line at a time from
memory, and issues one read per clock cycle.
■ Critical word first
Table 5–8 shows the instruction byte address fields.
The size of the tag field depends on the size of the cache memory and the
physical address size. The size of the line field depends only on the size
of the cache memory. The offset field is always three bits (i.e., an 8-word
line). The maximum instruction byte address size is 31 bits.
The instruction cache is optional. However, excluding instruction cache
from the Nios II/s core requires that the core include at least one tightly-
coupled instruction memory.
Tightly-Coupled Memory
The Nios II/s core provides optional tightly-coupled memory interfaces
for instructions. A Nios II/s core can use up to four tightly-coupled
instruction memories. When a tightly-coupled memory interface is
enabled, the Nios II core includes an additional memory interface master
port. Each tightly-coupled memory interface must connect directly to
exactly one memory slave port.
When tightly-coupled memory is present, the Nios II core decodes
addresses internally to determine if requested instructions reside in
tightly-coupled memory. If the address resides in tightly-coupled
memory, the Nios II core fetches the instruction through the tightly-
coupled memory interface. Software does not require awareness of
whether code resides in tightly-coupled memory or not.
Table 5–8. Instruction Byte Address Fields
31 . . . . . .543210
tag line offset 0 0