Specifications

5–14 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/s Core
Shift and Rotate Performance
The performance of shift operations depends on the hardware multiply
option. When a hardware multiplier is present, the ALU achieves shift
and rotate operations in three or four clock cycles. Otherwise, the ALU
includes dedicated shift circuitry that achieves one-bit-per-cycle shift and
rotate performance. Refer to Table 5–10 on page 5–17 for details.
Memory Access
The Nios II/s core provides instruction cache, but no data cache. The
instruction cache size is user-definable, between 512 bytes and 64 KBytes.
The Nios II/s core can address up to 2 Gbyte of external memory. The
Nios II architecture reserves the most-significant bit of data addresses for
the bit-31 cache bypass method. In the Nios II/s core, bit 31 is always
zero.
f For information regarding data cache bypass methods, refer to the
Processor Architecture chapter of the Nios II Processor Reference Handbook.
Instruction and Data Master Ports
The instruction port on the Nios II/s core is optional. The instruction
master port can be excluded, as long as the core includes at least one
tightly-coupled instruction memory. The instruction master port is a
pipelined Avalon-MM master port.
Support for pipelined Avalon-MM transfers minimizes the impact of
synchronous memory with pipeline latency. The pipelined instruction
master port can issue successive read requests before prior requests
complete.
The data master port on the Nios II/s core is always present.
Embedded multiplier on
Stratix, Stratix II and
Stratix III families
ALU includes 32 x 32-bit
multiplier
3
mul, muli, mulxss,
mulxsu, mulxuu
Embedded multiplier on
Cyclone II and Cyclone III
families
ALU includes 32 x 16-bit
multiplier
5
mul, muli
Hardware divide ALU includes multicycle
divide circuit
4 – 66
div, divu
Table 5–7. Hardware Multiply and Divide Details for the Nios II/s Core
ALU Option Hardware Details
Cycles per
instruction
Supported Instructions