Specifications

Altera Corporation 5–13
October 2007 Nios II Processor Reference Handbook
Nios II Core Implementation Details
The following sections discuss the noteworthy details of the Nios II/s
core implementation. This document does not discuss low-level design
issues, or implementation details that do not affect Nios II hardware or
software designers.
Arithmetic Logic Unit
The Nios II/s core provides several ALU options to improve the
performance of multiply, divide, and shift operations.
Multiply and Divide Performance
The Nios II/s core provides the following hardware multiplier options:
■ DSP Block — Includes DSP block multipliers available on the target
device. This option is available only on Altera FPGAs that have DSP
Blocks.
■ Embedded Multipliers — Includes dedicated embedded multipliers
available on the target device. This option is available only on Altera
FPGAs that have embedded multipliers.
■ Logic Elements— Includes hardware multipliers built from logic
element (LE) resources.
■ None — Does not include multiply hardware. In this case, multiply
operations are emulated in software.
The Nios II/s core also provides a hardware divide option that includes
LE-based divide circuitry in the ALU.
Including an ALU option improves the performance of one or more
arithmetic instructions.
1 The performance of the embedded multipliers differ, depending
on the target FPGA family.
Table 5–7 lists the details of the hardware multiply and divide options.
Table 5–7. Hardware Multiply and Divide Details for the Nios II/s Core
ALU Option Hardware Details
Cycles per
instruction
Supported Instructions
No hardware multiply or
divide
Multiply and divide
instructions generate an
exception
– None
LE-based multiplier ALU includes 32 x 4-bit
multiplier
11
mul, muli