Specifications

5–12 Altera Corporation
Nios II Processor Reference Handbook October 2007
Nios II/s Core
JTAG Debug Module
The Nios II/f core supports the JTAG debug module to provide a JTAG
interface to software debugging tools. The Nios II/f core supports an
optional enhanced interface that allows real-time trace data to be routed
out of the processor and stored in an external debug probe.
Unsupported Features
The Nios II/f core does not handle the execution of instructions with
undefined opcodes. If the processor issues an instruction word with an
undefined opcode, the resulting behavior is undefined.
Nios II/s Core
The Nios II/s “standard” core is designed for small core size. On-chip
logic and memory resources are conserved at the expense of execution
performance. The Nios II/s core uses approximately 20% less logic than
the Nios II/f core, but execution performance also drops by roughly 40%.
Altera designed the Nios II/s core with the following design goals in
mind:
■ Do not cripple performance for the sake of size.
■ Remove hardware features that have the highest ratio of resource
usage to performance impact.
The resulting core is optimal for cost-sensitive, medium-performance
applications. This includes applications with large amounts of code
and/or data, such as systems running an operating system where
performance is not the highest priority.
Overview
The Nios II/s core:
■ Has instruction cache, but no data cache
■ Can access up to 2 Gbytes of external address space
■ Supports optional tightly-coupled memory for instructions
■ Employs a 5-stage pipeline
■ Performs static branch prediction
■ Provides hardware multiply, divide, and shift options to improve
arithmetic performance
■ Supports the addition of custom instructions
■ Supports the JTAG debug module
■ Supports optional JTAG debug module enhancements, including
hardware breakpoints and real-time trace