Specifications

For example, in a 64-KB direct-mapped cache with a 16-byte line, bits 15:4 are used to select the line.
Assume that virtual address 0x1000 is mapped to physical address 0xF000 and virtual address 0x2000 is
also mapped to physical address 0xF000. This is an illegal virtual address alias because accesses to virtual
address 0x1000 use line 0x1 and accesses to virtual address 0x2000 use line 0x2 even though they map to
the same physical address. This results in two copies of the same physical address in the cache. With an n-
byte direct-mapped cache, there could be n/4096 copies of the same physical address in the cache if illegal
virtual address aliases are not prevented. The bits of the virtual address that are used to select the line and
are translated bits (bits 12 and up) are known as the color of the address. An operating system avoids
illegal virtual address aliases by ensuring that if multiple virtual addresses map the same physical address,
the virtual addresses have the same color. Note though, the color of the virtual addresses does not need to
be the same as the color as the physical address because the cache tag contains all the bits of the PFN.
Instruction Set Categories
This section introduces the Nios II instructions categorized by type of operation performed.
Data Transfer Instructions
The Nios II architecture is a load-store architecture. Load and store instructions handle all data
movement between registers, memory, and peripherals. Memories and peripherals share a common
address space. Some Nios II processor cores use memory caching and/or write buffering to improve
memory bandwidth. The architecture provides instructions for both cached and uncached accesses.
Table 3-41: Wide Data Transfer Instructions
Instruc‐
tion
Description
ldw
stw
The ldw and stw instructions load and store 32-bit data words from/to memory. The
effective address is the sum of a register's contents and a signed immediate value
contained in the instruction. Memory transfers can be cached or buffered to improve
program performance. This caching and buffering might cause memory cycles to occur
out of order, and caching might suppress some cycles entirely.
Data transfers for I/O peripherals should use ldwio and stwio.
ldwio
stwio
ldwio and stwio instructions load and store 32-bit data words from/to peripherals
without caching and buffering. Access cycles for ldwio and stwio instructions are
guaranteed to occur in instruction order and are never suppressed.
Table 3-42: Narrow Data Transfer Instructions
Instruction Description
ldb
ldbu
stb
ldh
ldhu
sth
ldb, ldbu, ldh and ldhu load a byte or half-word from memory to a register. ldb and
ldh sign-extend the value to 32 bits, and ldbu and ldhu zero-extend the value to 32 bits.
stb and sth store byte and half-word values, respectively.
Memory accesses can be cached or buffered to improve performance. To transfer data
to I/O peripherals, use the io versions of the instructions, described in the following
table cell.
3-60
Instruction Set Categories
NII51003
2015.04.02
Altera Corporation
Programming Model
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