Specifications

The Nios II architecture provides the following mechanisms to bypass the cache:
• When no MMU is present, bit 31 of the address is reserved for bit-31 cache bypass. With bit-31 cache
bypass, the address space of processor cores is 2 GB, and the high bit of the address controls the
caching of data memory accesses.
• When the MMU is present, cacheability is controlled by the MMU, and bit 31 functions as a normal
address bit. For details, refer to the Address Space and Memory Partitions section , and the TLB
Organization section of this chapter.
• Cache bypass instructions, such as ldwio and stwio.
Refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook for
details of which processor cores implement bit-31 cache bypass.
Refer to Instruction Set Reference chapter of the Nios II Processor Reference Handbook for details of the
cache bypass instructions.
Code written for a processor core with cache memory behaves correctly on a processor core without cache
memory. The reverse is not true. If it is necessary for a program to work properly on multiple Nios II
processor core implementations, the program must behave as if the instruction and data caches exist. In
systems without cache memory, the cache management instructions perform no operation, and their
effects are benign.
For a complete discussion of cache management, refer to theCache and Tightly Coupled Memory chapter
of the Nios II Software Developer’s Handbook.
Some consideration is necessary to ensure cache coherency after processor reset. Refer to "Reset
Exceptions" section of this chapter for more information.
For information about the cache architecture and the memory hierarchy refer to the Processor Architec‐
ture chapter of the Nios II Processor Reference Handbook.
Related Information
• Cache and Tightly Coupled Memory
• Reset Exceptions on page 3-39
• TLB Organization on page 3-5
• Address Space and Memory Partitions on page 3-4
• Instruction Set Reference on page 8-1
• Instruction Set Reference
• Processor Architecture on page 2-1
• Processor Architecture
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
Virtual Address Aliasing
A virtual address alias occurs when two virtual addresses map to the same physical address. When an
MMU and caches are present and the caches are larger than a page (4 KB), the operating system must
prevent illegal virtual address aliases. Because the caches are virtually-indexed and physically-tagged, a
portion of the virtual address is used to select the cache line. If the cache is 4 KB or less in size, the portion
of the virtual address used to select the cache line fits with bits 11:0 of the virtual address which have the
same value as bits 11:0 of the physical address (they are untranslated bits of the page offset). However, if
the cache is larger than 4 KB, bits beyond the page offset (bits 12 and up) are used to select the cache line
and these bits are allowed to be different than the corresponding physical address.
NII51003
2015.04.02
Virtual Address Aliasing
3-59
Programming Model
Altera Corporation
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