Specifications

Note: When the EIC interface and shadow register sets are implemented on the Nios II core, you must
ensure that your software, including ISRs, is built with the version of the GCC compiler included in
Nios II EDS version 9.0 or later. Earlier versions have an implementation of the eret instruction
that is incompatible with shadow register sets.
Related Information
Nested Exceptions with the Internal Interrupt Controller on page 3-54
Return Address Considerations
The return address requires some consideration when returning from exception processing routines.
After an exception occurs, ea contains the address of the instruction following the point where the
exception occurred.
When returning from instruction-related exceptions, execution must resume from the instruction
following the instruction where the exception occurred. Therefore, ea contains the correct return address.
On the other hand, hardware interrupt exceptions must resume execution from the interrupted instruc‐
tion itself. In this case, the exception handler must subtract 4 from ea to point to the interrupted instruc‐
tion.
Memory and Peripheral Access
Nios II addresses are 32 bits, allowing access up to a 4-gigabyte address space. Nios II core implementa‐
tions without MMUs restrict addresses to 31 bits or fewer. The MMU supports the full 32-bit physical
address.
For details, refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference
Handbook.
Peripherals, data memory, and program memory are mapped into the same address space. The locations
of memory and peripherals within the address space are determined at system generation time. Reading
or writing to an address that does not map to a memory or peripheral produces an undefined result.
The processor’s data bus is 32 bits wide. Instructions are available to read and write byte, half-word (16-
bit), or word (32-bit) data.
The Nios II architecture uses little-endian byte ordering. For data wider than 8 bits stored in memory, the
more-significant bits are located in higher addresses.
The Nios II architecture supports register and immediate addressing.
Related Information
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
Cache Memory
The Nios II architecture and instruction set accommodate the presence of data cache and instruction
cache memories. Cache management is implemented in software by using cache management instruc‐
tions. Instructions are provided to initialize the cache, flush the caches whenever necessary, and to bypass
the data cache to properly access memory-mapped peripherals.
3-58
Return Address Considerations
NII51003
2015.04.02
Altera Corporation
Programming Model
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