Specifications

The status.IL field controls what level of external maskable interrupts can be serviced. The processor
services a maskable interrupt only if its requested interrupt level is greater than status.IL.
An ISR can make run-time adjustments to interrupt nesting by manipulating status.IL. For example, if
an ISR is running at level 5, to temporarily allow pre-emption by another level 5 interrupt, it can set
status.IL to 4.
To enable all external interrupts, set status.IL to 0. To disable all external interrupts, set status.IL to
63.
Masking Interrupts with the Internal Interrupt Controller
The ienable register controls the handling of internal hardware interrupts. Each bit of the ienable
register corresponds to one of the interrupt inputs, irq0 through irq31. A value of one in bit n means
that the corresponding irqn interrupt is enabled; a bit value of zero means that the corresponding
interrupt is disabled.
Refer to the "Exception Processing" section of this chapter for more information.
An ISR can adjust ienable so that IRQs of equal or lower priority are disabled. Refer to the "Handling
Nested Exceptions" section of this chapter for more information.
Related Information
• Handling Nested Exceptions on page 3-54
• Exception Processing on page 3-36
Returning From Interrupt and Instruction-Related Exceptions
The eret instruction is used to resume execution at the pre-exception address.
You must ensure that when an exception handler modifies registers, they are restored when it returns.
This can be taken care of in either of the following ways:
• In the case of ISRs, if the EIC interface and shadow register sets are implemented, and the ISR has a
dedicated register set, no software action is required. The Nios II processor returns to the previous
register set when it executes eret, which restores the register contents.
• For details, refer to the "Nested Exceptions with an External Interrupt Controller" section of this
chapter.
• In the case of noninterrupt exceptions, for ISRs in a system with the internal interrupt controller, and
for ISRs without a dedicated shadow register set, the exception handler must save registers on entry
and restore them on exit. Saving the register contents on the stack is a typical, re-entrant implementa‐
tion.
Note:
It is not necessary to save and restore the exception temporary (et or r24) register.
When executing the eret instruction, the processor performs the following tasks:
1. Restores the previous contents of status as follows:
• If status.CRS is 0, copies estatus to status
• If status.CRS is nonzero, copies sstatus to status
2. Transfers program execution to the address in the ea register (r29) in the register set specified by the
original value of status.CRS.
Note:
The eret instruction can cause the processor to exit NMI mode. However, it cannot make the
processor enter NMI mode. In other words, if status.NMI is 0 and estatus.NMI (or
sstatus.NMI) is 1, after an eret, status.NMI is still 0. This restriction prevents the processor from
accidentally entering NMI mode.
NII51003
2015.04.02
Masking Interrupts with the Internal Interrupt Controller
3-57
Programming Model
Altera Corporation
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