Specifications

handle division error exception
else if (instruction is signed divide and numerator == 0x80000000
and denominator == 0xffffffff)
handle division error exception
}
}
/* Not any known exception */
} else {
handle unknown exception (If internal interrupt controller
is implemented, could be spurious interrupt)
}
}
Handling Nested Exceptions
The Nios II processor supports several types of nested exceptions, depending on which optional features
are implemented. Nested exceptions can occur under the following circumstances:
• An exception handler enables maskable interrupts
• An EIC is present, and an NMI occurs
• An EIC is present, and the processor is configured to keep maskable interrupts enabled when taking an
interrupt
• An exception handler triggers an instruction-related exception
For details about when the Nios II processor takes exceptions, refer to “Exception Processing Flow” on
page 3–44.
For details about unimplemented instructions, refer to the Processor Architecture chapter of the Nios II
Processor Reference Handbook.
For details about MMU and MPU exceptions, refer to the Instruction-Related Exceptions section of this
chapter.
A system can be designed to eliminate the possibility of nested exceptions. However, if nested exceptions
are possible, the exception handlers must be carefully written to prevent each handler from corrupting the
context in which a pre-empted handler runs.
If an exception handler issues a trap instruction, an optional instruction, or an instruction which could
generate an MMU or MPU exception, it must save and restore the contents of the estatus and ea
registers.
Related Information
• Exception Processing Flow on page 3-49
• Instruction-Related Exceptions on page 3-44
• Processor Architecture on page 2-1
• Processor Architecture
Nested Exceptions with the Internal Interrupt Controller
You can enable nested exceptions in each exception handler on a case-by-case basis. If you want to allow a
given exception handler to be pre-empted, set status.PIE to 1 near the beginning of the handler.
Enabling maskable interrupts early in the handler minimizes the worst-case latency of any nested
exceptions.
Note:
Ensure that all pre-empting handlers preserve the register contents.
3-54
Handling Nested Exceptions
NII51003
2015.04.02
Altera Corporation
Programming Model
Send Feedback