Specifications

Processor Status Register
or Field
System Status Before Taking Exception
External Interrupt Asserted
(18)
Internal Interrupt Asserted or Noninterrupt Exception
status.EH==1
(19)
status.EH==0
status.EH==1
status.EH==0
TLB
Miss
(21)
No TLB Miss
RRS==0
(2
0)
RRS!=0 RRS==0 RRS!=0 TLB Permission
Violation
(21)
No TLB
Permission
Violation
status.PIE
No change 0
(35)
status.EH
(19)
No change 1
(36)
status.IH
(37)
1 No change
status.NMI
(37)
RNMI No change
status.IL
(37)
RIL No change
status.RSIE
(20)(37)
0 No change
status.CRS
(20)
RRS No change
status.U
(19)
0
(38)
(18)
If the Nios II processor does not have an EIC interface, external interrupts do not occur.
(19)
If the Nios II processor does not have an MMU, this field is not implemented. Its value is always 0, and the
processor behaves accordingly.
(20)
If the Nios II processor does not have shadow register sets, this field is not implemented. Its value is always 0,
and the processor behaves accordingly.
(21)
If the Nios II processor does not have an MMU, TLB-related exceptions do not occur.
(22)
If the Nios II processor does not have an MMU, this register is not implemented.
(23)
The VPN of the address triggering the exception
(24)
The pre-exception value
(25)
Invokes the general exception handler
(26)
Invokes the fast TLB miss exception handler
(27)
If the Nios II processor does not have shadow register sets, this register is not implemented.
(28)
Saves the processor’s pre-exception status
(29)
sstatus.SRS is set to 1 if RRS is not equal to status.CRS.
(30)
The address following the instruction being executed when the exception occurs
(31)
Set to 1 on a data access exception, set to 0 otherwise
(32)
Set to 1 on a double TLB miss, set to 0 otherwise
(33)
Set to 1 on a TLB permission violation, set to 0 otherwise
(34)
Set to 1 on a bad virtual address exception, set to 0 otherwise
(35)
Disables exceptions and nonmaskable interrupts
(36)
If the MMU is implemented, indicates that the processor is handling an exception.
(37)
If the Nios II processor does not have an EIC interface, this field is not implemented.
(38)
Puts the processor in supervisor mode.
3-52
Exceptions and Processor Status
NII51003
2015.04.02
Altera Corporation
Programming Model
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