Specifications
Exception Flow with the Internal Interrupt Controller
A general exception handler determines which of the pending interrupts has the highest priority, and then
transfers control to the appropriate ISR. The ISR stops the interrupt from being visible (either by clearing
it at the source or masking it using ienable) before returning and/or before re-enabling PIE. The ISR also
saves estatus and ea (r29) before re-enabling PIE.
Interrupts can be re-enabled by writing one to the PIE bit, thereby allowing the current ISR to be
interrupted. Typically, the exception routine adjusts ienable so that IRQs of equal or lower priority are
disabled before re-enabling interrupts.
Refer to "Handling Nested Exceptions” for more information.
Related Information
Handling Nested Exceptions on page 3-54
Exceptions and Processor Status
The Nios II Processor Status After Taking Exception Table lists all changes to the Nios II processor state
as a result of nonbreak exception processing actions performed by hardware. For systems with an MMU,
status.EH indicates whether or not exception processing is already in progress. When status.EH = 1,
exception processing is already in progress and the states of the exception registers are preserved to retain
the original exception states.
Table 3-38: Nios II Processor Status After Taking Exception
Processor Status Register
or Field
System Status Before Taking Exception
External Interrupt Asserted
(18)
Internal Interrupt Asserted or Noninterrupt Exception
status.EH==1
(19)
status.EH==0
status.EH==1
status.EH==0
TLB
Miss
(21)
No TLB Miss
RRS==0
(2
0)
RRS!=0 RRS==0 RRS!=0 TLB Permission
Violation
(21)
No TLB
Permission
Violation
pteaddr.VPN
(22)
No change VPN
(23)
No change
status.PRS
(20)
No change
status.CRS
(20)
(24)
No change
pc
RHA General
exception
vector
(25)
Fast TLB
exception
vector
(26)
General exception vector
(20)
sstatus
(27)(28)
No change
status
(24)(29)
No change
estatus
(28)
No change
status
(24)
No change
status
(24)
ea
No change return address
(30)
No change return address
tlbmisc.D
(19)
No change
(31)
tlbmisc.DBL
(19)
No change
(32)
tlbmisc.PERM
(19)
No change
(33)
tlbmisc.BAD
(19)
No change
(34)
NII51003
2015.04.02
Exception Flow with the Internal Interrupt Controller
3-51
Programming Model
Altera Corporation
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