Specifications

Introduction
1
2015.04.02
NII51001
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This handbook describes the Nios
®
II Classic processor from a high-level conceptual description to the
low-level details of implementation. The chapters in this handbook describe the Nios II processor
architecture, the programming model, and the instruction set. The Nios II Classic processor is only
avaliable in the Quartus II 14.0 release and below.
This handbook assumes you have a basic familiarity with embedded processor concepts. You do not need
to be familiar with any specific Altera technology or with Altera development tools. This handbook limits
discussion of hardware implementation details of the processor system. The Nios II processors are
designed for Altera
®
FPGA devices, and so this handbook does describe some FPGA implementation
concepts. Your familiarity with FPGA technology provides a deeper understanding of the engineering
trade-offs related to the design and implementation of the Nios II processor.
This chapter introduces the Altera Nios II embedded processor family and describes the similarities and
differences between the Nios II processor and traditional embedded processors.
Related Information
Literature: Nios II Processor
This handbook is the primary reference for the Nios II family of embedded processors and is part of a
larger collection of documents covering the Nios II processor and its usage that you can find on the
Literature: Nios II Processor Page of the Altera website.
Nios II Processor System Basics
The Nios II processor is a general-purpose RISC processor core with the following features:
• Full 32-bit instruction set, data path, and address space
• 32 general-purpose registers
• Optional shadow register sets
• 32 interrupt sources
• External interrupt controller interface for more interrupt sources
• Single-instruction 32 × 32 multiply and divide producing a 32-bit result
• Dedicated instructions for computing 64-bit and 128-bit products of multiplication
• Optional floating-point instructions for single-precision floating-point operations
• Single-instruction barrel shifter
• Access to a variety of on-chip peripherals, and interfaces to off-chip memories and peripherals
• Hardware-assisted debug module enabling processor start, stop, step, and trace under control of the
Nios II software development tools
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