Specifications

A data address is considered misaligned if the byte address is not a multiple of the width of the load or
store instruction data width (four bytes for word, two bytes for half-word). Byte load and store instruc‐
tions are always aligned so never take a misaligned address exception.
Related Information
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
Misaligned Destination Address
The Nios II processor can check for misaligned destination addresses of the callr, jmp, ret, eret, bret,
and all branch instructions and generate an exception when a misaligned destination address is
encountered. When your system contains an MMU or MPU, misaligned destination address checking is
always on. When no MMU or MPU is present, you have the option to have the processor check for
misaligned destination addresses.
For information about controlling this option, refer to the Instantiating the Nios II Processor chapter of
the Nios II Processor Reference Handbook.
A destination address is considered misaligned if the target byte address of the instruction is not a
multiple of four.
Related Information
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
Division Error
The Nios II processor can check for division errors and generate an exception when a division error is
encountered.
For information about controlling this option, refer to the Instantiating the Nios II Processor chapter of
the Nios II Processor Reference Handbook.
The division error exception detects divide instructions that produce a quotient that can't be represented.
The two cases are divide by zero and a signed division that divides the largest negative number
-2147483648 (0x80000000) by -1 (0xffffffff). Division error detection is only available if divide instruc‐
tions are supported by hardware.
Related Information
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
Fast TLB Miss
Fast TLB miss exceptions are implemented only in Nios II processors that include the MMU. The MMU
has a special exception vector (fast TLB miss), specified with the Nios II Processor parameter editor in
Qsys, specifically to handle TLB miss exceptions quickly. Whenever the processor cannot find a TLB entry
matching the VPN (optionally extended by a process identifier), the result is a TLB miss exception. At the
time of the exception, the processor first checks status.EH. When status.EH = 0, no other exception is
already in process, so the processor considers the TLB miss a fast TLB miss, sets status.EH to one, and
transfers control to the fast TLB miss exception handler (rather than to the general exception handler).
NII51003
2015.04.02
Misaligned Destination Address
3-47
Programming Model
Altera Corporation
Send Feedback