Specifications

Note: All undefined opcodes are reserved. The processor does occasionally use some undefined
encodings internally. Executing one of these undefined opcodes does not trigger an illegal instruc‐
tion exception.
Refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook for
information about each specific Nios II core.
Related Information
• Instruction Set Reference on page 8-1
• Instruction Set Reference
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
• Nios II Core Implementation Details on page 5-1
• Nios II Core Implementation Details
Supervisor-Only Instruction
When your system contains an MMU or MPU and the processor is in user mode (status.U = 1),
executing a supervisor-only instruction results in a supervisor-only instruction exception. The supervisor-
only instructions are initd, initi, eret, bret, rdctl, and wrctl.
This exception is implemented only in Nios II processors configured to use supervisor mode and user
mode. Refer to the "Operating Modes" section of this chapter for more information.
Related Information
Operating Modes on page 3-1
Supervisor-Only Instruction Address
When your system contains an MMU and the processor is in user mode (status.U = 1), attempts to
access a supervisor-only instruction address result in a supervisor-only instruction address exception. Any
instruction fetch can cause this exception. For definitions of supervisor-only address ranges, refer to the
Virtual Memory Partitions Table.
This exception is implemented only in Nios II processors that include the MMU.
Related Information
Virtual Memory Address Space on page 3-4
Supervisor-Only Data Address
When your system contains an MMU and the processor is in user mode (status.U = 1), any attempt to
access a supervisor-only data address results in a supervisor-only data address exception. Instructions that
can cause a supervisor-only data address exception are all loads, all stores, and flushda.
This exception is implemented only in Nios II processors that include the MMU.
Misaligned Data Address
The Nios II processor can check for misaligned data addresses of load and store instructions and generate
an exception when a misaligned data address is encountered. When your system contains an MMU or
MPU, misaligned data address checking is always on. When no MMU or MPU is present, you have the
option to have the processor check for misaligned data addresses.
For information about controlling this option, refer to the Instantiating the Nios II Processor chapter of
the Nios II Processor Reference Handbook.
3-46
Supervisor-Only Instruction
NII51003
2015.04.02
Altera Corporation
Programming Model
Send Feedback