Specifications

Figure 3-2: Relationship Between ienable, ipending, PIE and Hardware Interrupts
IPENDING0
IPENDING1
IPENDING2
ipending Register
IPENDING31
irq0
irq1
irq2
irq31
013
IENABLE0
IENABLE1
IENABLE2
013
ienable Register
External hardware
interrupt request
inputs irq[31..0]
. . .
. . .
. . .
PIE bit
Generate
Hardware
Interrupt
IENABLE31
Related Information
Exception Processing Flow on page 3-49
Instruction-Related Exceptions
Instruction-related exceptions occur during execution of Nios II instructions. When they occur, the
processor perform the steps outlined in the "Exception Processing Flow" section of this chapter.
The Nios II processor generates the following instruction-related exceptions:
• Trap instruction
• Break instruction
• Unimplemented instruction
• Illegal instruction
• Supervisor-only instruction
• Supervisor-only instruction address
• Supervisor-only data address
• Misaligned data address
• Misaligned destination address
• Division error
3-44
Instruction-Related Exceptions
NII51003
2015.04.02
Altera Corporation
Programming Model
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