Specifications

For the best interrupt performance, assign a dedicated register set to each of the most time-critical
interrupts. Less-critical interrupts can share register sets, provided the ISRs are protected from register
corruption as noted in the Requested Register Set section of this chapter.
The method for mapping interrupts to register sets is specific to the particular EIC implementation.
Related Information
Requested Register Set on page 3-42
Internal Interrupt Controller
When the internal interrupt controller is implemented, a peripheral device can request a hardware
interrupt by asserting one of the Nios II processor’s 32 interrupt-request inputs, irq0 through irq31. A
hardware interrupt is generated if and only if all three of these conditions are true:
• The PIE bit of the status control register is one.
• An interrupt-request input, irqn, is asserted.
• The corresponding bit n of the ienable control register is one.
Upon hardware interrupt, the processor clears the PIE bit to zero, disabling further interrupts, and
performs the other steps outlined in the "Exception Processing Flow" section of this chapter.
The value of the ipending control register shows which interrupt requests (IRQ) are pending. By
peripheral design, an IRQ bit is guaranteed to remain asserted until the processor explicitly responds to
the peripheral.
Note:
Although shadow register sets can be implemented in any Nios II/f processor, the internal
interrupt controller does not have features to take advantage of it as external interrupt controllers
do.
NII51003
2015.04.02
Internal Interrupt Controller
3-43
Programming Model
Altera Corporation
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