Specifications

• Requested Register Set on page 3-42
• Requested Interrupt Level on page 3-42
Requested Handler Address
The RHA specifies the address of the handler associated with the interrupt. The availability of an RHA for
each interrupt allows the Nios II processor to jump directly to the interrupt handler, reducing interrupt
latency.
The RHA for each interrupt is typically software-configurable. The method for specifying the RHA is
dependent on the specific EIC implementation.
If the Nios II processor is implemented with an MMU, the processor treats handler addresses as virtual
addresses.
Requested Interrupt Level
The Nios II processor uses the RIL to decide when to take a maskable interrupt. The interrupt is taken
only when the RIL is greater than status.IL.
The RIL is ignored for nonmaskable interrupts.
Requested Register Set
If shadow register sets are implemented on the Nios II core, the EIC specifies a register set when it asserts
an interrupt request. When it takes the interrupt, the Nios II processor switches to the requested register
set. When an interrupt has a dedicated register set, the interrupt handler avoids the overhead of saving
registers.
The method of assigning register sets to interrupts depends on the specific EIC implementation. Register
set assignments can be software-configurable.
Multiple interrupts can be configured to share a register set. In this case, the interrupt handlers must be
written so as to avoid register corruption. For example, one of the following conditions must be true:
• The interrupts cannot pre-empt one another. For example, all interrupts are at the same level.
• Registers are saved in software. For example, each interrupt handler saves its own registers on entry,
and restores them on exit.
Typically, the Nios II processor is configured so that when it takes an interrupt, other interrupts in the
same register set are disabled. If interrupt preemption within a register set is desired, the interrupt handler
can re-enable interrupts in its register set.
By default, the Nios II processor disables maskable interrupts when it takes an interrupt request. To
enable nested interrupts, system software or the ISR itself must re-enable interrupts after the interrupt is
taken.
Requested NMI Mode
Any interrupt can be nonmaskable, depending on the configuration of the EIC. An NMI typically signals
a critical system event requiring immediate handling, to ensure either system stability or real-time
performance.
status.IL and RIL are ignored for nonmaskable interrupts.
Shadow Register Sets
Although shadow register sets can be implemented independently of the EIC interface, typically the two
features are used together. Combining shadow register sets with an appropriate EIC, you can minimize or
eliminate the context switch overhead for critical interrupts.
3-42
Requested Handler Address
NII51003
2015.04.02
Altera Corporation
Programming Model
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