Specifications

The reset state is undefined for all other system components, including but not limited to:
• General-purpose registers, except for zero (r0) in the normal register set, which is permanently zero.
• Control registers, except for status. status.RSIE is reset to 1, and the remaining fields are reset to 0.
• Instruction and data memory.
• Cache memory, except for the instruction cache line associated with the reset vector.
• Peripherals. Refer to the appropriate peripheral data sheet or specification for reset conditions.
• Custom instruction logic
• Nios II C-to-hardware (C2H) acceleration compiler logic.
For more information refer to the Nios II Custom Instruction User Guide for reset conditions.
Related Information
Nios II Custom Instruction User Guide
Break Exceptions
A break is a transfer of control away from a program’s normal flow of execution for the purpose of
debugging. Software debugging tools can take control of the Nios II processor via the JTAG debug
module.
Break processing is the means by which software debugging tools implement debug and diagnostic
features, such as breakpoints and watchpoints. Break processing is a type of exception processing, but the
break mechanism is independent from general exception processing. A break can occur during exception
processing, enabling debug tools to debug exception handlers.
The processor enters the break processing state under either of the following conditions:
• The processor executes the break instruction. This is often referred to as a software break.
• The JTAG debug module asserts a hardware break.
Processing a Break
A break causes the processor to take the following steps:
1. Stores the contents of the status register to bstatus.
2. Clears status.PIE to zero, disabling maskable interrupts.
Note:
Nonmaskable interrupts (NMIs) are not affected by status.PIE, and can be taken while
processing a break exception.
1. Writes the address of the instruction following the break to the ba register (r30) in the normal
register set.
2. Clears status.U to zero, forcing the processor into supervisor mode, when the system contains
an MMU or MPU.
3. Sets status.EH to one, indicating the processor is handling an exception, when the system
contains an MMU.
4. Copies status.CRS to status.PRS and then sets status.CRS to 0.
5. Transfers execution to the break handler, stored at the break vector specified in the Nios II
Processor parameter editor.
Note:
All noninterrupt exception handlers, including the break handler, must run in the normal register
set.
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Break Exceptions
NII51003
2015.04.02
Altera Corporation
Programming Model
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