Specifications
Exception Type Available Cause Address Vector
MPU region
violation (data)
Instruction-
related
MPU 17 badaddr (data
address)
General exception
Related Information
• Requested Handler Address on page 3-42
• General-Purpose Registers on page 3-10
Exception Latency
Exception latency specifies how quickly the system can respond to an exception. Exception latency
depends on the type of exception, the software and hardware configuration, and the processor state.
Interrupt Latency
The interrupt controller can mask individual interrupts. Each interrupt can have a different maximum
masked time. The worst-case interrupt latency for interrupt i is determined by that interrupt’s maximum
masked time, or by the maximum disabled time, whichever is greater.
Reset Exceptions
When a processor reset signal is asserted, the Nios II processor performs the following steps:
1. Sets status.RSIE to 1, and clears all other fields of the status register.
2. Invalidates the instruction cache line associated with the reset vector.
3. Begins executing the reset handler, located at the reset vector.
Note:
All noninterrupt exception handlers must run in the normal register set.
Clearing the status.PIE field disables maskable interrupts. If the MMU or MPU is present, clearing the
status.U field forces the processor into supervisor mode.
Note:
Nonmaskable interrupts (NMIs) are not affected by status.PIE, and can be taken while
processing a reset exception.
Invalidating the reset cache line guarantees that instruction fetches for reset code comes from uncached
memory.
Aside from the instruction cache line associated with the reset vector, the contents of the cache memories
are indeterminate after reset. To ensure cache coherency after reset, the reset handler located at the reset
vector must immediately initialize the instruction cache. Next, either the reset handler or a subsequent
routine should proceed to initialize the data cache.
(14)
It is possible for any instruction fetch to cause this exception.
(15)
Refer to the Nios II General-Purpose Registers Table for descriptions of the ea and ba registers.
(16)
For a description of the requested handler address, refer to the Requested Handler Address section of this
chapter.
NII51003
2015.04.02
Exception Latency
3-39
Programming Model
Altera Corporation
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