Specifications

The following table columns specify information for the exceptions:
• Exception—Gives the name of the exception.
• Type—Specifies the exception type.
• Available—Specifies when support for that exception is present.
• Cause—Specifies the value of the CAUSE field of the exception register, for exceptions that write the
exception.CAUSE field.
• Address—Specifies the instruction or data address associated with the exception.
• Vector—Specifies which exception vector address the processor passes control to when the exception
occurs.
Table 3-36: Nios II Exceptions (In Decreasing Priority Order)
Exception Type Available Cause Address Vector
Reset Reset Always 0 Reset
Hardware break Break Always — Break
Processor-only reset
request
Reset Always 1 Reset
Internal interrupt Interrupt Internal
interrupt
controller
2 ea–4
(15)
General exception
External nonmask‐
able interrupt
Interrupt External
interrupt
controller
interface
— ea–4
(15)
Requested handler
address
(16)
External maskable
interrupt
Interrupt External
interrupt
controller
interface
2 ea–4
(15)
Requested handler
address
(16)
ECC TLB error
(instruction)
Instruction-
related
MMU and
ECC
18 ea–4
(15)
General exception
Supervisor-only
instruction
address
(14)
Instruction-
related
MMU 9 ea–4
(15)
General exception
Fast TLB miss
(instruction)
(14)
Instruction-
related
MMU 12 pteaddr.VPN,
ea–4
(15)
Fast TLB Miss
exception
Double TLB miss
(instruction)
(14)
Instruction-
related
MMU 12 pteaddr.VPN,
ea–4
(15)
General exception
TLB permission
violation (execute)
(14)
Instruction-
related
MMU 13 pteaddr.VPN,
ea–4
(15)
General exception
ECC register file
error
Instruction-
related
ECC 20 ea–4
(15)
General exception
MPU region
violation (instruc‐
tion)
(14)
Instruction-
related
MPU 16 ea–4
(15)
General exception
NII51003
2015.04.02
Exception Overview
3-37
Programming Model
Altera Corporation
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