Specifications

Instruction Cache Tag RAM
1. Ensure all code up to the JMP instruction is in the same instruction cache line or is located in an
ITCM.
2. Use a FLUSHI instruction to flush an instruction cache line other than the line containing the executing
code.
3. Use a FLUSHP instruction to flush the pipeline.
4. Use a WRCTL instruction to set ECCINJ.ICTAG to INJS or INJD. This setting causes an ECC error to
occur on the start of the next line fill.
5. Use a JMP instruction to jump to an instruction address in the flushed line.
6. The ECC error is injected when writing the tag RAM at the start of the line fill.
7. Use a RDCTL instruction to ensure that the value of ECCINJ.ICTAG is NOINJ.
8. The ECC error triggers after the target of the JMP instruction.
Instruction Cache Data RAM
1. Ensure all code up to the JMP instruction is in the same instruction cache line or is located in an
ITCM.
2. Use a FLUSHI instruction to flush an instruction cache line other than the line containing the executing
code.
3. Use a FLUSHP instruction to flush the pipeline.
4. Use a WRCTL instruction to set ECCINJ.ICDAT to INJS or INJD. This setting causes an ECC error to
occur on the start of the next line fill.
5. Use a JMP instruction to jump to an instruction address in the flushed line.
6. The ECC error is injected when writing the tag RAM at the start of the line fill.
7. Use a RDCTL instruction to ensure that the value of ECCINJ.ICDAT is NOINJ.
8. Execute the target of the JMP instruction twice (first to inject the ECC error and second to be triggered
by it).
Register File RAM Blocks
1. Use a WRCTL instruction to set ECCINJ.RF to INJS or INJD (as desired).
2. Execute any instruction that writes any register except R0.
3. Use a RDCTL instruction to ensure that the value of ECCINJ.RF is NOINJ.
4. Use an instruction to read the desired register from rA such as OR rd, r0, rx where rx is the register
written in the previous step. This action triggers the ECC error.
5. Use an instruction to read the desired register from rB such as OR rd, rx, r0 where rx is the register
written in the previous step.
MMU TLB RAM
1. Use a WRCTL instruction to set ECCINJ.TLB to INJS or INJD.
2. Use a WRCTL instruction to write a TLB entry. The ECC error will be injected at this time and any
associated uTLB entry will be flushed.
3. Use a RDCTL instruction to ensure the value of ECCINJ.TLB is NOINJ.
4. Perform an instruction/data access to cause the hardware to read the TLB entry (copied into uTLB)
and the ECC decoder should detect the ECC error at this time. Alternatively, initiate a software read of
the TLB (by writing TLBMISC.RD to 1).
5. If a software read was initiated, the TLBMISC.EE field should be set to 1 on any instruction after the
WRCTL that triggered the software read.
6. If a hardware read was initiated, the ECC error should be triggered on the first instruction after the
hardware read.
NII51003
2015.04.02
Instruction Cache Tag RAM
3-35
Programming Model
Altera Corporation
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