Specifications

Working with ECC
Enabling ECC
The ECC is disabled on system reset. Before enabling the ECC, initialize the Nios II RAM blocks to avoid
spurious ECC errors.
The Nios II processor executes the INITI instruction on each cache line, which initializes the instruction
cache RAM. The RAM does not require special initialization because any detected ECC errors are ignored
if the line is invalid; the line is invalid after INITI instructions initialize the tag RAM.
Nios II processor instructions that write to every register (except register 0) initialize the register file RAM
blocks. If shadow register sets are present, this step is performed for all registers in the shadow register set
using the WRPRS instruction.
Nios II processor instructions that write every TLB RAM location initialize the MMU TLB RAM. This
RAM does not require special initialization.
Disabling ECC
Disable ECC in software by writing 0 to CONFIG.ECCEN. Software can re-enable ECC without reinitializing
the ECC-protected RAMs because the ECC parity bits are written to the RAM blocks even if ECC is
disabled.
Handling ECC Errors
ECC error exceptions occur when unrecoverable ECC errors are detected. The software’s ability to recover
from the ECC error depends on the nature of the error.
Typically, software can recover from an unrecoverable MMU TLB ECC error (2 bit error) because the
TLB is a software-managed cache of the operating system page tables stored in the main memory (e.g.,
SDRAM). Software can invalid the TLB entry, return to the instruction that took the ECC error exception,
and execute the TLB’s mishandled code to load a TLB entry from the page tables.
In general, software cannot recover from a register file ECC error (2 bit error) because the correct value of
a register is not known. If the exception handler reads a register that has a 2 bit ECC error associated with
it, another ECC error occurs and an exception handler loop can occur.
Exception handler loops occur when an ECC error exception occurs in the exception handler before it is
ready to handle nested exceptions. To minimize the occurrence or exception handler loops, locate the
ECC error exception handler code in normal cacheable memory, ensure that all data accesses are to non-
cacheable memory, and minimize register reading.
The ECC error signals (ecc_event_bus) provide the EEH signal for external logic to detect a possible
exception handler loop and reset the Nios II processor.
Injecting ECC Errors
This section describes the code sequence for injecting ECC errors for each ECC-protected RAM,
assuming the ECC is enabled and interrupts are disabled for the duration of the code sequence.
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Working with ECC
NII51003
2015.04.02
Altera Corporation
Programming Model
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