Specifications

Bit Description Access Reset Available
RSIE RSIE is the register set interrupt-
enable bit. When set to 1, this bit
allows the processor to service
external interrupts requesting the
register set that is currently in use.
When set to 0, this bit disallows
servicing of such interrupts.
Read/Write Undefined
(13)
NMI NMI is the nonmaskable interrupt
mode bit. The processor sets NMI to 1
when it takes a nonmaskable
interrupt.
Read/Write Undefined
(13)
PRS
(13)
Read/Write Undefined
(13)
CRS
(13)
Read/Write Undefined
(13)
IL
(13)
Read/Write Undefined
(13)
IH
(13)
Read/Write Undefined
(13)
EH
(13)
Read/Write Undefined
(13)
U
(13)
Read/Write Undefined
(13)
PIE
(13)
Read/Write Undefined
(13)
The sstatus register is present in the Nios II core if both the EIC interface and shadow register sets are
implemented. There is one copy of sstatus for each shadow register set.
When the Nios II processor takes an interrupt, if a shadow register set is requested (RRS = 0) and the
MMU is not in exception handler mode (status.EH = 0), the processor copies status to sstatus.
For details about RRS, refer to "Requested Register Set”.
For details about status.EH, refer to the Nios II Processor Status After Taking Exceptions Table.
Related Information
• The status Register on page 3-13
• Exceptions and Processor Status on page 3-51
• Requested Register Set on page 3-42
• The status Register on page 3-13
Changing Register Sets
Modifying status.CRS immediately switches the Nios II processor to another register set. However,
software cannot write to status.CRS directly. To modify status.CRS, insert the desired value into the
saved copy of the status register, and then execute the eret instruction, as follows:
(12)
Refer to the status Control Register Field Descriptions Table
(13)
If the EIC interface and shadow register sets are not present, SRS always reads as 0, and the processor behaves
accordingly.
NII51003
2015.04.02
Changing Register Sets
3-31
Programming Model
Altera Corporation
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