Specifications
When shadow register sets are implemented, status.CRS indicates the register set currently in use. A
Nios II core can have up to 63 shadow register sets. If n is the configured number of shadow register sets,
the shadow register sets are numbered from 1 to n. Register set 0 is the normal register set.
A shadow register set behaves precisely the same as the normal register set. The register set currently in
use can only be determined by examining status.CRS.
Note: When shadow register sets and the EIC interface are implemented on the Nios II core, you must
ensure that your software is built with the Nios II EDS version 9.0 or later. Earlier versions have an
implementation of the eret instruction that is incompatible with shadow register sets.
Shadow register sets are typically used in conjunction with the EIC interface. This combination can
substantially reduce interrupt latency.
For details of EIC interface usage, refer to the Exception Processing section.
System software can read from and write to any shadow register set by setting status.PRS and using the
rdprs and wrprs instructions.
For details of the rdprs and wrprs instructions, refer to the Instruction Set Reference chapter of the Nios II
Processor Reference Handbook.
Related Information
• Instruction Set Reference on page 8-1
• Instruction Set Reference
• Exception Processing on page 3-36
The sstatus Register
The value in the sstatus register preserves the state of the Nios II processor during external interrupt
handling. The value of sstatus is undefined at processor reset. Some bits are exclusively used by and
available only to certain features of the processor.
The sstatus register is physically stored in general-purpose register r30 in each shadow register set. The
normal register set does not have an sstatus register, but each shadow register set has a separate sstatus
register.
Table 3-34: sstatus Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRS Reserved RSIE NMI PRS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRS IL IH EH U PIE
Table 3-35: sstatus Control Register Field Descriptions
Bit Description Access Reset Available
SRS
(13)
SRS is the switched register set bit.
The processor sets SRS to 1 when an
external interrupt occurs, if the
interrupt required the processor to
switch to a different register set.
Read/Write Undefined EIC interface and
shadow register sets
only
3-30
The sstatus Register
NII51003
2015.04.02
Altera Corporation
Programming Model
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