Specifications

The MT Flag
The MT flag determines the default memory type of an MPU data region. . The MT flag only applies to data
regions. For instruction regions, the MT bit must be written with 0 for instruction regions and is always
read as 0.
When data cacheability is enabled on a data region, a data access to that region can be cached, if a data
cache is present in the system. You can override the default cacheability and force an address to
noncacheable with an ldio or stio instruction. The encoding of the MT field is setup to be backwards-
compatible with the Nios II Classic core MPU where bit 5 of MPUACC contains the cacheable bit (0 =
non-cacheable, 1 = cacheable) and bit 6 is zero.
Note: The bit 31 cache bypass feature is supported when the MPU is present. Refer to the Cache memory
section for more information on cache bypass.
The PERM Field
The PERM field specifies the allowed access permissions.
Table 3-30: Instruction Region Permission Values
Value Supervisor Permissions User Permissions
0 None None
1 Execute None
2 Execute Execute
Table 3-31: Data Region Permission Values
Value Supervisor Permissions User Permissions
0 None None
1 Read None
2 Read Read
4 Read/Write None
5 Read/Write Read
6 Read/Write Read/Write
Note: Unlisted table values are reserved and must not be used. If you use reserved values, the resulting
behavior is undefined.
The RD Flag
Setting the RD flag signifies that an MPU region read operation should be performed when a wrctl
instruction is issued to the mpuacc register. Refer to the MPU Region Read and Write Operations section
for more information. The RD flag always returns 0 when read by a rdctl instruction.
Related Information
MPU Region Read and Write Operations on page 3-32
3-28
The MT Flag
NII51003
2015.04.02
Altera Corporation
Programming Model
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