Specifications

MASK Encoding Region Size
0x1FFFC00 64 KB
0x1FFF800 128 KB
0x1FFF000 256 KB
0x1FFE000 512 KB
0x1FFC000 1 MB
0x1FF8000 2 MB
0x1FF0000 4 MB
0x1FE0000 8 MB
0x1FC0000 16 MB
0x1F80000 32 MB
0x1F00000 64 MB
0x1E00000 128 MB
0x1C00000 256 MB
0x1800000 512 MB
0x1000000 1 GB
0x0000000 2 GB
The MASK field contains the following value, where region_size is in bytes:
MASK = 0x1FFFFFF << log2(region_size >> 6)
The LIMIT Field
When the amount of memory reserved for a region is defined by an upper address limit, the LIMIT field
specifies the upper address of the memory region plus one. For example, to achieve a memory range for
byte addresses 0x4000 to 0x4fff with a 256 byte minimum region size, the BASE field of the mpubase
register is set to 0x40 (0x4000 >> 6) and the LIMIT field is set to 0x50 (0x5000 >> 6). Because the LIMIT
field is one more bit than the number of bits of the BASE field of the mpubase register, bit 31 of the mpuacc
register is available to the LIMIT field.
The C Flag
The C flag determines the default data cacheability of an MPU region. The C flag only applies to data
regions. For instruction regions, the C bit must be written with 0 and is always read as 0.
When data cacheability is enabled on a data region, a data access to that region can be cached, if a data
cache is present in the system. You can override the default cacheability and force an address to
noncacheable with an ldio or stio instruction.
Note:
The bit 31 cache bypass feature is supported when the MPU is present. Refer to the Cache memory
section for more information on cache bypass.
Related Information
Cache Memory on page 3-58
NII51003
2015.04.02
The LIMIT Field
3-27
Programming Model
Altera Corporation
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