Specifications

Field Description Access Reset Available
PERM PERM specifies the access permissions for the region. Read/
Write
0 Only with MPU
RD RD is the read region flag. When RD = 1, wrctl
instructions to the mpuacc register perform a read
operation.
Write 0 Only with MPU
WR WR is the write region flag. When WR = 1, wrctl
instructions to the mpuacc register perform a write
operation.
Write 0 Only with MPU
The MASK and LIMIT fields are mutually exclusive. Refer to mpucc Control Register Field for MASK
Variation Table and mpuacc Control Register Field for LIMIT Variation Table.
The following sections provide more information about the mpuacc fields.
Related Information
• The LIMIT Field on page 3-27
• The MASK Field on page 3-26
The MASK Field
When the amount of memory reserved for a region is defined by size, the MASK field specifies the size of
the memory region. The MASK field is the same number of bits as the BASE field of the mpubase register.
Note:
Unused high-order or low-order bits must be written as zero and are read as zero.
MASK Region Size Encodings Table lists the MASK field encodings for all possible region sizes in a full 31-
bit byte address space.
Table 3-29: MASK Region Size Encodings
MASK Encoding Region Size
0x1FFFFFF 64 bytes
0x1FFFFFE 128 bytes
0x1FFFFFC 256 bytes
0x1FFFFF8 512 bytes
0x1FFFFF0 1 KB
0x1FFFFE0 2 KB
0x1FFFFC0 4 KB
0x1FFFF80 8 KB
0x1FFFF00 16 KB
0x1FFFE00 32 KB
(11)
This field size is variable. Unused upper bits and unused lower bits must be written as zero.
3-26
The MASK Field
NII51003
2015.04.02
Altera Corporation
Programming Model
Send Feedback