Specifications
The INDEX and D fields specify the region information to access when an MPU region read or write
operation is performed. The D field specifies whether the region is a data region or an instruction region.
The INDEX field specifies which of the 32 data or instruction regions to access. If there are fewer than 32
instruction or 32 data regions, unused high-order bits must be written as zero and are read as zero.
Refer to the MPU Region Read and Write Operations section for more information on MPU region read
and write operations.
Related Information
MPU Region Read and Write Operations on page 3-32
The mpuacc Register
The mpuacc register works in conjunction with the mpubase register to set and retrieve MPU region
information and is only available in systems with an MPU. The mpuacc register consists of attributes that
will be set or have been retrieved which define the MPU region. The mpuacc register only holds a portion
of the attributes that define an MPU region. The remaining portion of the MPU region definition is held
by the BASE field of the mpubase register.
A Qsys generation-time option controls whether the mpuacc register contains a MASK or LIMIT field.
Table 3-26: mpuacc Control Register Fields for MASK Variation
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK
(11)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK
(11)
C PERM RD WR
Table 3-27: mpuacc Control Register Fields for LIMIT Variation
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LIMIT
(11)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LIMIT
(11)
C PERM RD WR
Table 3-28: mpuacc Control Register Field Descriptions
Field Description Access Reset Available
MASK MASK specifies the size of the region. Read/
Write
0 Only with MPU
LIMIT LIMIT specifies the upper address limit of the region. Read/
Write
0 Only with MPU
C C is the data cacheable flag. C only applies to MPU data
regions and determines the default cacheability of a data
region. When C = 0, the data region is uncacheable.
When C = 1, the data region is cacheable.
Read/
Write
0 Only with MPU
NII51003
2015.04.02
The mpuacc Register
3-25
Programming Model
Altera Corporation
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