Specifications

Field Description Access Reset Available
ECCEXE ECCEX is the ECC error exception enable bit. When
ECCEXE = 1, the Nios II processor generates ECC error
exceptions.
Read/Write 0 Only
with
ECC
ECCEN ECCEN is the ECC enable bit. When ECCEN = 0, the Nios II
processor ignores all ECC errors. When ECCEN = 1, the
Nios II processor recovers all recoverable ECC errors.
Read/Write 0 Only
with
ECC
PE PE is the memory protection enable bit. When PE =1, the
MPU is enabled. When PE = 0, the MPU is disabled. In
systems without an MPU, PE is always zero.
Read/Write 0 Only
with
MPU
The mpubase Register
The mpubase register works in conjunction with the mpuacc register to set and retrieve MPU region
information and is only available in systems with an MPU.
Table 3-24: mpubase Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 BASE
(10)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BASE
(10)
INDEX
(9)
D
Table 3-25: mpubase Control Register Field Descriptions
Field Description Access Reset Available
BASE BASE is the base memory address of the region identified
by the INDEX and D fields.
Read/
Write
0 Only with MPU
INDEX INDEX is the region index number. Read/
Write
0 Only with MPU
D D is the region access bit. When D =1, INDEX refers to a
data region. When D = 0, INDEX refers to an instruction
region.
Read/
Write
0 Only with MPU
The BASE field specifies the base address of an MPU region. The 25-bit BASE field corresponds to bits 6
through 30 of the base address, making the base address always a multiple of 64 bytes. If the minimum
region size set in Qsys at generation time is larger than 64 bytes, unused low-order bits of the BASE field
must be written as zero and are read as zero. For example, if the minimum region size is 1024 bytes, the
four least-significant bits of the BASE field (bits 6 though 9 of the mpubase register) must be zero.
Similarly, if the Nios II address space is less than 31 bits, unused high-order bits must also be written as
zero and are read as zero.
(9)
This field size is variable. Unused upper bits must be written as zero.
(10)
This field size is variable. Unused upper bits and unused lower bits must be written as zero.
3-24
The mpubase Register
NII51003
2015.04.02
Altera Corporation
Programming Model
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