Specifications
Table 3-21: badaddr Control Register Field Descriptions
Field Description Access Reset Available
BADDR BADDR contains the byte instruction address or data
address associated with an exception when certain
exceptions occur. The Address column of the Nios II
Exceptions Table lists which exceptions write the BADDR
field.
Read 0 Only with extra
exception
information
The BADDR field allows up to a 32-bit instruction address or data address. If an MMU or MPU is present,
the BADDR field is 32 bits because MMU and MPU instruction and data addresses are always full 32-bit
values. When an MMU is present, the BADDR field contains the virtual address.
If there is no MMU or MPU and the Nios II address space is less than 32 bits, unused high-order bits are
written and read as zero. If there is no MMU, bit 31 of a data address (used to bypass the data cache) is
always zero in the BADDR field.
Related Information
• Exception Overview on page 3-36
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
The config Register
The config register configures Nios II runtime behaviors that do not need to be preserved during
exception processing (in contrast to the information in the status register).
Table 3-22: config Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved ECCEX
E
ECCE
N
ANI PE
Table 3-23: config Control Register Field Descriptions
Field Description Access Reset Available
ANI ANI is the automatic nested interrupt mode bit. If ANI is
set to zero, the processor clears status.PIE on each
interrupt, disabling fast nested interrupts. If ANI is set to
one, the processor keeps status.PIE set to one at the
time of an interrupt, enabling fast nested interrupts.
If the EIC interface and shadow register sets are not
implemented in the Nios II core, ANI always reads as
zero, disabling fast nested interrupts.
Read/Write 0 Only
with the
EIC
interface
and
shadow
register
sets
NII51003
2015.04.02
The config Register
3-23
Programming Model
Altera Corporation
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