Specifications

Refer to Nios II Exceptions (In Decreasing Priority Order) table in the "Exception Overview" section for
more information on these exceptions.
Related Information
Exception Overview on page 3-36
The PERM Flag
During a general exception, the processor sets PERM to one for a TLB permission violation exception, and
clears PERM to zero otherwise.
The D Flag
The D flag indicates whether the exception is an instruction access exception or a data access exception.
During a general exception, the processor sets D to one when the exception is related to a data access, and
clears D to zero for all other nonbreak exceptions.
The following exceptions set the D flag to one:
• Fast TLB miss (data)
• Double TLB miss (data)
• TLB permission violation (read or write)
• Misaligned data address
• Supervisor-only data address
The badaddr Register
When the extra exception information option is enabled, the Nios II processor provides information
useful to system software for exception processing in the exception and badaddr registers when an
exception occurs. When your system contains an MMU or MPU, the extra exception information is
always enabled. When no MMU or MPU is present, the Nios II Processor parameter editor gives you the
option to have the processor provide the extra exception information.
For information about controlling the extra exception information option, refer to the Instantiating the
Nios II Processor chapter of the Nios II Processor Reference Handbook.
When the option for extra exception information is enabled and a processor exception occurs, the
badaddr register contains the byte instruction or data address associated with certain exceptions at the
time the exception occurred. The Nios II Exceptions Table lists which exceptions write the badaddr
register along with the value written.
Table 3-20: badaddr Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BADDR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BADDR
3-22
The PERM Flag
NII51003
2015.04.02
Altera Corporation
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