Specifications

When system software changes the fields that specify the TLB entry, there is no immediate effect on
pteaddr.VPN, tlbmisc.PID, or the tlbacc register. The registers retain their previous values until the
next TLB read operation is initiated. For example, when the operating system sets pteaddr.VPN to a new
value, the contents of tlbacc continues to reflect the previous TLB entry. tlbacc does not contain the
new TLB entry until after an explicit TLB read.
The WE Flag
When WE = 1, a write to tlbacc writes the tlbacc register and a TLB entry. When WE = 0, a write to
tlbacc only writes the tlbacc register.
Hardware sets the WE flag to one on a TLB permission violation exception, and on a TLB miss exception
when status.EH = 0. When a TLB write operation writes the tlbacc register, the write operation also
writes to a TLB entry when WE = 1.
The WAY Field
The WAY field controls the mapping from the VPN to a particular TLB entry. WAY specifies the set to be
written to in the TLB. The MMU increments WAY when system software performs a TLB write operation.
Unused upper bits in WAY must be written as zero.
Note:
The number of ways (sets) is configurable in Qsys at generation time, up to a maximum of 16.
The PID Field
PID is a unique identifier for the current process that effectively extends the virtual address. The process
identifier can be less than 14 bits. Any unused upper bits must be zero.
tlbmisc.PID contains the PID field from a TLB tag. The operating system must set the PID field when
switching processes, and before each TLB write operation.
Note:
Use of the process identifier is optional. To implement memory management without process
identifiers, clear tlbmisc.PID to zero. Without a process identifier, all processes share the same
virtual address space.
The MMU sets tlbmisc.PID on a TLB read operation. When the software triggers a TLB read, by setting
tlbmisc.RD to one with the wrctl instruction, the PID value read from the TLB has priority over the value
written by the wrctl instruction.
The size of the PID field is configured in Qsys at system generation, and can be from 8 to 14 bits. If system
software defines a process identifier smaller than the PID field, unused upper bits must be written as zero.
The DBL Flag
During a general exception, the processor sets DBL to one when a double TLB miss condition exists.
Otherwise, the processor clears DBL to zero.
The DBL flag indicates whether the most recent exception is a double TLB miss condition. When a general
exception occurs, the MMU sets DBL to one if a double TLB miss is detected, and clears DBL to zero
otherwise.
The BAD Flag
During a general exception, the processor sets BAD to one when a bad virtual address condition exists, and
clears BAD to zero otherwise. The following exceptions set the BAD flag to one:
• Supervisor-only instruction address
• Supervisor-only data address
• Misaligned data address
• Misaligned destination address
NII51003
2015.04.02
The WE Flag
3-21
Programming Model
Altera Corporation
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