Specifications

Bit Fields
Reserved EE WAY RD WE PID
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PID DBL BAD PERM D
Table 3-19: tlbmisc Control Register Field Descriptions
Field Description Access Reset Available
EE If this field is a 1, a software-triggered ECC error (1, 2, or
3 bit error) occurred because software initiated a TLB
read operation. Only set this field to 1 if CONFIG.ECCEN is
1.
Read/
Write
0 Only with MMU
and EEC
WAY The WAY field controls the mapping from the VPN to a
particular TLB entry.
This field size is variable. Unused upper bits must be
written as zero.
Read/
Write
0 Only with MMU
RD RD is the read flag. Setting RD to one triggers a TLB read
operation.
Write 0 Only with MMU
WE WE is the TLB write enable flag. When WE = 1, a write to
tlbacc writes through to a TLB entry.
Read/
Write
0 Only with MMU
PID PID is the process identifier field.
This field size is variable. Unused upper bits must be
written as zero.
Read/
Write
0 Only with MMU
DBL DBL is the double TLB miss exception flag. Read 0 Only with MMU
BAD BAD is the bad virtual address exception flag. Read 0 Only with MMU
PERM PERM is the TLB permission violation exception flag. Read 0 Only with MMU
D D is the data access exception flag. When D = 1, the
exception is a data access exception. When D = 0, the
exception is an instruction access exception.
Read 0 Only with MMU
For DBL, BAD, and PERM fields you can also use exception.CAUSE to determine these exceptions.
The following sections provide more information about the tlbmisc fields.
The RD Flag
System software triggers a TLB read operation by setting tlbmisc.RD (with a wrctl instruction). A TLB
read operation loads the following register fields with the contents of a TLB entry:
• The tag portion of pteaddr.VPN
• tlbmisc.PID
• The tlbacc register
The TLB entry to be read is specified by the following values:
• the line portion of pteaddr.VPN
• tlbmisc.WAY
3-20
The RD Flag
NII51003
2015.04.02
Altera Corporation
Programming Model
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