Specifications

Related Information
• Instantiating the Nios II Processor on page 4-1
• Instantiating the Nios II Processor
The pteaddr Register
The pteaddr register contains the virtual address of the operating system’s page table and is only available
in systems with an MMU. The pteaddr register layout accelerates fast TLB miss exception handling.
Table 3-14: pteaddr Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PTBASE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPN Rsvd
Table 3-15: pteaddr Control Register Field Descriptions
Field Description Access Reset Available
PTBASE PTBASE is the base virtual address of the page table. Read/
Write
0 Only
with
MMU
VPN VPN is the virtual page number. VPN can be set by both
hardware and software.
Read/
Write
0 Only
with
MMU
Software writes to the PTBASE field when switching processes. Hardware never writes to the PTBASE field.
Software writes to the VPN field when writing a TLB entry. Hardware writes to the VPN field on a fast TLB
miss exception, a TLB permission violation exception, or on a TLB read operation. The VPN field is not
written on any exceptions taken when an exception is already active, that is, when status.EH is already
one.
The tlbacc Register
The tlbacc register is used to access TLB entries and is only available in systems with an MMU. The
tlbacc register holds values that software will write into a TLB entry or has previously read from a TLB
entry. The tlbacc register provides access to only a portion of a complete TLB entry. pteaddr.VPN and
tlbmisc.PID hold the remaining TLB entry fields.
Table 3-16: tlbacc Control Register Fields
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IG C R W X G PFN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PFN
3-18
The pteaddr Register
NII51003
2015.04.02
Altera Corporation
Programming Model
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